Delay lines are widely used in a variety of integrated circuit (IC) applications, such as delay or phase-locked loops (PLLs), clock generators, or frequency synthesizers. The delay line is typically formed on an IC by cascading a string of digital signal, or digital logic, inverters, each connection or coupling between the inverters serving as a "tap" along the delay line. One method of controlling the amount of delay through the delay line involves varying ("starving") the power supply current supplied to the digital signal inverters. Another technique involves varying the amount of capacitive loading at the output port of the inverters, such as illustrated in U.S. Pat. No. 5,012,142, assigned to the assignee of the present invention and herein incorporated by reference.
One drawback of the delay control approaches described above is the inability of the propagation delay in the delay line to be as short as the technology used to implement the delay line permits. For example, the delay for a current "starved" inverter based delay line may be significantly longer than if the inverters are not current limited. Further, if the current "starving" is accomplished by decreasing the power supply current, as the inverter is current "starved" to increase the delay, the voltage amplitude swing of signals propagating through the inverters may decrease, thus having the undesirable effect of actually reducing, rather than increasing, the propagation delay.
A ring oscillator may be formed from a delay line by coupling the input port of an active delay line to its output port. This technique, for example, is widely used in IC PLLs. Such ring oscillators typically have an odd number of digital signal inverters or inverting delay stages serially connected or coupled so as to form a ring oscillator configuration. The oscillation frequency is substantially determined by the propagation delay of the digital signal inverters.
The propagation delay for a digital signal inverter in the ring oscillator may be controlled by the techniques described above. Nonetheless, these approaches have several drawbacks, much like the drawbacks described above with respect to delay lines. First, the highest oscillation frequency of the ring oscillator may be considerably less than the oscillation frequencies possible with the technology used to implement the oscillator, such as CMOS technology. Second, these delay control approaches, in particular current "starving" the inverter, may exhibit uncontrolled signal amplitudes, possibly leading to a nonmonotonic frequency versus voltage characteristic and, likewise, degrading oscillator performance. Third, these delay techniques, such as current "starving" the inverters, frequently require narrowly controlled bias currents, often achieved by using a voltage-to-current signal converter, for satisfactory operation. Thus, a need exists for a digital signal inverter for use in ring oscillators and delay lines that reduces the foregoing problems.